A Serial Infrared Remote Control Receiver

Receiver Schematic Note - this is a scan of a hand-drawn circuit. Sorry about the low quality; I haven't gotten around to redoing it with CAD tools.

This circuit is used to receive and demodulate an IR remote control signal. The resulting data stream is then transmitted via an RS-232 port to whatever system is waiting for it.

Overall Circuit Operation

The IR carrier state is sampled at periodic intervals, with the sampling frequency high enough that the structure and specific values of the IR codes can be determined. The samples are stored in a shift register. After each 8 samples have been stored, data from that shift register is transferred to another shift register to be retransmitted via RS-232 at twice the rate at which the signal is sampled. The purpose of the deserialization followed by serialization is to allow the transmission to occur at twice the sampling frequency, which in turn provides “time space” for the RS-232 start and stop bits to be added.

Main Data Path

A GP1U252(1X), GP1U5(21X), or equivalent IR receiver module (manufactured by Sharp, sold by Radio Shack at last check) receives and demodulates the 40 kHz IR signal. This gives a signal that is high when there is no carrier present and low when carrier is present. This is inverted (to high when carrier is present) by U1A, of a CD4093B (quad NAND Shmitt trigger). This is fed to an 8-bit serial-in, parallel-out shift register (both halves of a CD4015B dual 4-bit shift register connected together to form an 8-bit shift register). The parallel output of this is fed to 8 bits of a 16-bit parallel-in serial-out shift register formed from two CD4014B 8-bit shift registers. An input bit at one end of the PISO shift register is connected to logic low and 7 input bits at the other end of the shift register are connected to logic high. These form the start bit and 7 stop bits respectively (only one stop bit is needed, but making the entire frame be 16 bits simplifies the circuit design). When the data is clocked out of the PISO shift register, these two “end” bits form the RS-232 start and stop bits. The output of the PISO shift register is fed to a MAX232 for translation to RS-232 voltage levels, impedance, and slew rates. Its output is connected to the TX pin of a 9-pin (or 25-pin) DSUB connector.

Transmitter Enable / Keepalive

The output of U1A (the demodulated IR signal, inverted so that carrier present results in a logic high) is also fed to a retriggerable one-shot formed from a diode, resistor, capacitor, and another Schmitt trigger. The output of this will be low whenever an IR signal is being detected, and for some time afterwards. This is used to enable the RS-232 transmitter circuit for long enough after the last IR data was received for that data to be fully transmitted before the transmitter is disabled. While the one-shot output is low, the transmitter clock is enabled. When it is high, the transmitter clock is disabled, and further all of the registers are cleared, ensuring that no spurious data is transmitted the next time carrier is detected.

Transmitter Clock / Framing

The transmitter clock is a classic Shmitt oscillator formed from U1C. Since it uses a NAND gate, it is disabled by bringing the extra gate input low. It drives the PISO register and so sets the Baud rate of the serial output. The values given are intended to be used to set a 38400 Baud data rate, and the potentiometer should be adjusted to give a frequency of 38400 Hz. Since the last data bit ends 9 bit-times after the start of the start bit, and the last bit will be sampled by the receiver near the center of its bit time, and each data frame is followed by an extended off time, the frequency need only be accurate to within a few percent, making an RC oscillator sufficient.

The transmitter clock also drives a framing counter formed from of a CD4520 dual 4-bit counter. Note that the enable input of this counter is being used as a clock input. The 1 output of the counter, which gives the input clock divided by 2, in turn drives the clock input of the SIPO register, causing it to sample the IR data stream at the rate at which data will be clocked out. The rate using the described components and adjustment will be 19200 samples per second, which gives about one sample for each two cycles of 40 kHz IR carrier, and has been found sufficient for all remote controls examined. Transmitting data at twice the sample rate leaves time for the start and stop bits to be added.

When the framing counter reaches 15, the SIPO register will have been clocked 8 times and so will have loaded 8 IR samples. At this count, U2A causes the PISO register to load all 16 of its bits, transferring the 8 samples along with start and stop bits to the PISO register to be transmitted over the serial line.

This web page maintained by John DuBois