Chaper 6

Intels 8088 8 bit micro-processor
-----------------------------------

The 8088 micro-processor is a 40 pin HMOS TTL type chip utilizing a single 5 volt power supply source. IBM calls it a 16 bit processor, but in reality it is only an 8 bit processor. This discrepancy comes from the fact that it only has 8 data pins on the outside, but it has 16 bit data registers on the inside. In other words, the data is actually transferred on the system board 8 bits at a time but the data is operated on 16 bits at a time inside the 8088 registers. There are several registers inside the 8088 that are used to hold data and or to modify it on a temporary basis. These registers can be thought of as 16 bit d latches or 16 bit JK flip-flops. After an operation is preformed on the data in one of the registers, it must be moved to a location in ram, for a more permanent type of storage until it is saved to a disk file.


8088 8-BIT HMOS MICROPROCESSOR
-------------------------------

8 BIT DATA BUS INTERFACE
8 - 16 BIT INTERNAL REGISTERS
DIRECT ADDRESSING OF 1 MEG MEMORY
14 WORKING REGISTERS (16 BITS)
BYTE,WORD AND BLOCK OPERATIONS
2 CLOCK RATES (4.77 MHZ AND 8 MHZ)


PIN FUNCTION DESCRIPTION

SYMBOL PIN # TYPE NAME AND FUNCTION
--------------------------------------------------

AD7-AD0:9-16 I/O ADDRESS DATA BUS: These pins are the time multiplexed memory/IO address and data lines.

A15-A8:2-8,39 O ADDRESS BUS: These pins provide address bits 8 through 15 for the entire bus cycle.


A19/S6:5-38 O ADDRESS/ STATUS: These pins are the
A18/S5 4 most significant address lines for
A17/S4 memory operations.
A16/S3


__
RD: 32 O RESD: Read strobe indicates that the processor is performing a memory or IO read cycle, depending on the state of the IO/M pin or S2.


READY: 22 I READY: is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer. The RDY signal from I/O or memory is synchronized by the 8284 clock generator to form READY.
INTR: 18 I INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector look-up table located in system memory. It can be internally masked by software re-setting the interrupt enable bit.


TEST: 23 I TEST: input is examined by the "wait for test" instruction. If the TEST input is low, execution continues, otherwise the processor waits in an "idle" state.


NMI 7 I NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector look-up table located in system memory. This in-put is not maskable by software.


RESET 21 I RESET: causes the processor to terminate its present activity. Must be active high for at least four clock cycles.


CLK: 19 I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle.


VCC: 40 VCC: is the +5 V +/- 10% power supply pin.


GND 1,20 GND: are ground pins.

MN/MX: 33 I MINIMUM/MAXIMUM: indicates what mode the processor is in.

Memory organization
--------------------
The 8088 provides a 20 bit address to memory which locates the byte being selected. This memory is arranged as a block of up to 1 megabyte, addressed as 00000(H) to FFFFF(H). This memory is further divided into smaller blocks called segments, that are 64K bytes per segment. There are four segment types called CODE, DATA, EXTRA and STACK that are used for the data and code of a program. Addressing memory is accomplished through the use of one of four high speed segment registers called CS, DS, ES, and SS in combination with an IP register (instruction pointer). The segment register points to the segment in memory being used and the IP register points to an offset within that segment. See Fig.X & X



The registers are divided into groups that is based on what they are used for. General purpose registers are 16 bits or 8 bits

The 8088 instruction set (41 instructions)
------------------------------------------


Data transfer instructions Arithmetic instructions
-------------------------- -----------------------
MOV----------------------move------------------------ADD----------- addition
PUSH, POP------------stack operation----------INC------------ increment
XCHG---------------------exchange-----------------SUB------------subtract
IN,OUT-------------------input/output-------------DEC------------decrement
------------------------------------------------------------NEG-------------negate (two's comp)
------------------------------------------------------------CMP-------------compare
------------------------------------------------------------MUL-------------multiply
------------------------------------------------------------DIV--------------divide



Logical instructions-------------------------String instructions

NOT----------complement---------------------MOVS---- move string
AND----------and------------------------------CMPS---- compare string
OR------------inclusive or----------------------SCAS----- scan string
XOR----------exclusive or---------------------LODS----- load from a string
TEST---------test bits--------------------------STOS----- store into string
SHL,SHR---shift left/right
ROL,ROR---rotate left/right


Transfer of control instructions
--------------------------------
CALL-------------goto a sub-routine
RET---------------return from a sub-routine
JMP---------------jump
JZ,JNZ-----------conditional jumps
LOOP-------------iteration
LOOPNE---------conditional iteration
INT----------------interrupt
IRET--------------return from interrupt


PROCESSOR CONTROL
---------------------------------
CLC,STC------------clear/set flags
HLT-------------------halt CPU

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