AMPRO LITTLE BOARD Z80 I/O and MEMORY MAP The Ampro Little Board Z80 EPROM is initially imaged in the lowest 4KB's and this is reflected ambiguously 8 times, up to the 32K boundary. After boot the lower 32K DRAM is mapped in, for a total of 64KB and the EPROM is inaccessible thereafter in CP/M without a lot of care, that is! I managed it and pirated a copy into a soft loader for use of the monitor EPROM (different than the boot EPROM, a bonus) in software. Ask if you want a copy by email or in an EPROM and give me your address! There is an 8-bit control register located at I/O 00Hex. All bits are cleared at reset. These are: Bit 7 6 5 4 3 2 1 0 BCR X EEN DDEN SD1 DS4 DS3 DS2 DS1 --------------------------------------------- Where: X = don't care EEN EPROM enable 0=enabled in lower 32KB 1= disabled, replaced by DRAM DDEN = Double-Density enable 0=enabled 1=disabled SD1 = Side 1, 1=floppy side 1 , of two (0 and 1, 0=bottom) DS4, DS3, DS2, DS1 Floppy Drive Selects -------- The CTC chip has four independent counter/timers at 40H, 50H, 60H, and 70H in I/O space. It's master clock is the 4MHz system and the 2MHz clock is the counting clock. These are CTC channels 0, 1, 2, 3 in that order above in the successive I/O addresses. Channel 0 is the baudrate generator for DART channel A, serial port A Channel 1 is the baudrate generator for DART channel B, serial port B Channel 2 is unused, and is available for user applications. Channel 3 can be used as an optional interrupt for the FDC logic. The Little Board BIOS doesn't support this use, however. -------- The DART talks to the serial ports A and B through four non-consecutive I/O addresses, 80H, 84H, 88H, and 8CH, which are: Data A Control A Data B and Control B -------- Floppy Disk Controller I/O Addresses: C0H Command Register Write C1H Track Register Write C2H Sector Register Write C3H Data Register Write C4H Status Register Read C5H Track Register Read C6H Sector Register Read C7H Data Register Read The DS1-4 of the board control register BCR also are used, of course, as is the Drive Ready line from the drives to the DART DCDB input pin. -------- Parallel Port 01H I/O address is the data register for the printer data pins. 02H Any write to this I/O address sets the strobe flip-flop. 03H Any write to this I/O address clears the strobe flip-flop. The BUSY signal, pin 10, is connected to the DART RIB input, and the DART channel B status register is read for RIB status. You must first send the DART a channel B "reset external status" command to correctly read the BUSY signal. RIB is inverted so that BUSY = 0 is RIB HI. -------- That's it, except to check for ambiguous I/O addressing. The ambiguities are listed as follows: --------------------------------------------- Board Control Register 000xxx00 Parallel Port Data Latch 000xxx01 Parallel Strobe Set 000xxx10 Parallel Strobe Clear 000xxx11 CTC 01xxxxxx DART 10xxxxxx FDC 11xxxxxx Unused, available to user 0011xxxx Unused, reserved 0010xxxx ---------------------------------------------- Well, that's it, Ed! Hope you enjoyed it. ;-> -Steve Walz rstevew@armory.com Santa Cruz, CA