Clock, Reset and other bits around the CPU

Originally, the clock circuit was made from a 2MHz cyrstal, two capacitors, two resistors and an inverter. A textbook crystal oscillator, but I'm a chemist not an electronic engineer so I don't really understand it. When the computer didn't work this was my first suspect, so I replaced it with an all-in-one 4-pin TTL crystal oscillator module. It seems that no-one makes 2MHz modules, so I had to settle for 1MHz. Naturally, the computer still didn't work, so I built a little programmable clock module using the rather expensive Epson SPG8640BN. This provides 57 frequencies between 0.0083Hz and 1MHz, and is programmed with a 6-way DIP switch.

The reset circuit has also been changed. To begin with I used a capacitor and a couple of resistors in a configuration stolen from someone else's design. I wasn't 100% convinced about this arrangement, so I now just use a DS1813 EconoReset IC. This comes in a 3-pin transistor style package, connects to +5V, GND and RES, and pulses the RES line on power-up, power-down and when you press a button connected from RES to GND.

Also around the CPU are some 3k3 pull-up resistors on the IRQ, NMI and RDY pins.

Address Decoding

The A15 line is connected straight to the chip select pin of the RAM. Hence, if A15 is low (access to bottom 32k of memory) then the RAM is selected. The R/W line is connected to the RAM's write enable, and through an inverter (1/4 74LS00) to output enable.

If A15 is high, then the 74LS138 (3-to-8 decoder) is enabled and looks at A12-A14. The eight outputs correspond to 4k blocks of memory in the range $8000-$FFFF.

Outputs 6 and 7 of the '138 ($E000-$FFFF) are combined by an AND gate (made from 1/2 of a 74LS00) to provide the chip select for the EEPROM. This needs some thinking about, due to the active-low inputs and outputs. Chip select and output enable are tied together and write enable tied high, because we only ever want to read from this device, never write.

Output 5 of the '138 selects the 4k of I/O space at $D000-$DFFF. This activates the 74LS154 (4-to-16 decoder) which looks at A8-A11 to divide the I/O space into sixteen 256-byte segments. Each of the sixteen outputs will act as chip select for a particular I/O device.

The VIAs and ACIA

There are two 6522 VIAs. Their chip selects are connected to outputs 1 and 2 of the 74LS154, which maps them to $D100 and $D200. They have the usual connections to the address, data and control busses, and all their I/O lines are made available on PCB connectors.

The 6551 ACIA is connected up in a similar way to the VIAs, and is mapped to $D000. A 1.8432MHz crystal with a 33pF trimming capacitor is connected between XTAL1 and XTAL2 - this is used to produce the various baud rates. Two RS232 output lines (TXD, DTR) and two RS232 input lines (RXD, DSR) are made available to the outside world via a MAX232CPE. This device converts 0V/5V logic level signals to RS232 levels (about +10V/-10V I think). A few capacitors are needed between certain pins as shown on the data sheet.

Other Little Bits

Well, there's the power indicator. I use a nice bright blue LED (is this the first computer with a blue power LED?) with a 150 ohm series resistor. This value was scientifically determined (sort of) from the quoted forward voltage in the catalogue, and some equation which escapes me right now.

There is also a handful of 0.1uF ceramic capacitors spread about the place. Specifically, there's one as close as possible to each chip (bar one or two) to do that decoupling thing across the power rails.