To View the Funny Old DOS Line-Box characters, use QuickView on the Windows right-click menu with "Terminal" Font, or else MS-DOS EDIT, also the Viewer in WinZip works. ------------- page 1 кФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФП Г ASTATER.EXE Version 1.0 - AHDL State Machine Generator Г РФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФФй (C)Copyright & Support - Amos Zaslavsky @ 972-4-230219. Description ........................................................ 1 Command line syntax ................................................ 2 Example 1 : A Mealy machine with fully encoded state assignment .... 3 Example 2 : A Mealy machine with One-Hot state assignment .......... 11 Example 3 : A Moore machine with direct outputs .................... 15 Example 4 : A Moore mixed example .................................. 21 Errors, Warning & Note Messages .................................... 28 Limitations & Legal details ........................................ 32 Description ------------- ASTATER.EXE is a utility for generating an ABEL file for state machines. It will generate a file template that will fit your requirements of: - number of inputs - number of outputs - maximum number of relevant conditions per state - number of flip flops - state names After generation of the state machine file you will have to make a few changes to the file with your text editor. This utility can save time and let you concentrate on the logic of the machine an not on the syntax. The program is simpler to use then some fancy graphical state machine generators that are on the market (which are also expensive). The original idea of a stater program came from Ofer Hoffman (A VHDL shark @ 972-4-230048) how wrote a program like this for VHDL users ! page 2 Command line syntax --------------------- ASTATER must be followed by eight command line parameters: ASTATER /1|2 ... Is the module name. This will also be the file name and device name. Is the number of inputs. At least one input must be defined. Number of indirect outputs. Indirect output is an output that is not a direct flip flop output. Is the maximum number of relevant condition per state. A machine can have many inputs (for example 15: I1,I2...I15), but in each state only a small number of conditions is relevant. for example: condition1 - I1 & !I2 condition2 - I1 & I2 condition3 - !I1 (in this example only 3 conditions). The maximum number of conditions is 2^(inputs). A condition is not only a single input signal (literal) but a can be a function of such signals (Like in the previous example). Number of flip-flops. A state machine must have at least one flip-flop. If it has no flip-flops it is not a synchronous state machine. If you plan to use one of the Flip-Flop outputs as an output of the machine (a good way to prevent output spikes), don't count it as an output of the machine. Such an output is called in this document - "A direct output". Only indirect outputs should be counted as outputs of the machine. /1|2 Type of machine: /1 - Moore machine (outputs depend only of the present state of the machine) /2 - Mealy machine (outputs depend both on the present state of the machine and the inputs) /3 - Dummy machine (A moore machine that can be compiled with on modifications. The machine is a cyclic counter enabled by the "input1" signal. The number of conditions that you enter as command line is not relevant.) A state name. A list of state names must have at least tow members, but can have more. page 3 Example 1 : A Mealy machine with fully encoded state assignment --------------------------------------------------------------- In this example we will describe a Mealy state machine with 3 inputs and 3 outputs. кФФФФФФФФФП U ФФФ>Д УФФ>Ф R Inputs V ФФФ>Д M1 УФФ>Ф S Outputs W ФФФ>Д УФФ>Ф T РФФФФТФФФФй Г Cp ФФ>ФФй This is a state-table of the machine: кФФФФФФФФФФФФФФФТФФФФФФФФФТТФФФФФФФФФФФФФФФТФФФФФФФФФП Г Present State Г Input ГГ Next State Г Output Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г AA Г !U ГГ AA Г R Г Г Г U ГГ BB Г R Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г BB Г !V ГГ CC Г S,T Г Г Г V ГГ DD Г S Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г CC Г !V & W ГГ CC Г - Г Г Г V & W ГГ DD Г - Г Г Г !W ГГ AA Г - Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г DD Г 1 ГГ AA Г R,S Г РФФФФФФФФФФФФФФФСФФФФФФФФФССФФФФФФФФФФФФФФФСФФФФФФФФФй It is easy to see from the table that the maximum number of transition conditions per state is three. The behavior of this machine is a Mealy behavior only when the machine is in state BB (and it's enough to make it a Mealy machine). When the machine is in state DD it makes an un-conditional transition (Autonomous) to the AA state. In This example we will use a full binary encoding of state assignments. For this kind of encoding we need only tow flip-flops. In the next example we will use a One-Hot decoded state assignments. In the next example four flip-flops will be needed. page 4 For this example ASTATER.EXE will be used with The following command line parameters: 3 - inputs 3 - outputs 3 - conditions 2 - flip-flops /2 - Mealy machine AA - first state BB - second state CC - third state DD - forth state Here is the command line you have to type: ASTATER M1 3 3 3 2 /2 AA BB CC DD Here is the file that will be created by ASTATER.EXE : M1.ABL кФ ГMODULE M1 ГTITLE 'M1.ABL created by ASTATER.EXE Version 1.0 Г Time of creation is Sat Aug 20 17:07:13 1994 Г ' ГDECLARATIONS Г Г M1 DEVICE ; Г input1 PIN ; Г input2 PIN ; Г input3 PIN ; Г CP PIN ; "CLOCK INPUT" Г MR PIN ; "MASTER RESET (ASYN) INPUT" Г output1 PIN ISTYPE 'COM' ; Г output2 PIN ISTYPE 'COM' ; Г output3 PIN ISTYPE 'COM' ; Г Q1 NODE ISTYPE 'REG,BUFFER' ; Г Q0 NODE ISTYPE 'REG,BUFFER' ; Г Г PS = [Q1,Q0] ; "STATE ASSIGNMENT" Г AA = [ 0, 0] ; Г BB = [ 0, 0] ; Г CC = [ 0, 0] ; Г DD = [ 0, 0] ; Г Г C , X , P , Z = .C. , .X. , .P. , .Z. ; Г page 5 ГEQUATIONS Г ГPS.AR = !MR ; Г PS.CLK = CP ; Г ГSTATE_DIAGRAM PS Г Г STATE AA : Г [output1,output2,output3]=[0,0,0] ; Г CASE Г condition11 : next_state11 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г condition12 : next_state12 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г condition13 : next_state13 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г ENDCASE ; Г STATE BB : Г [output1,output2,output3]=[0,0,0] ; Г CASE Г condition21 : next_state21 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г condition22 : next_state22 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г condition23 : next_state23 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г ENDCASE ; Г STATE CC : pgage 6 Г [output1,output2,output3]=[0,0,0] ; Г CASE Г condition31 : next_state31 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г condition32 : next_state32 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г condition33 : next_state33 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г ENDCASE ; Г STATE DD : Г [output1,output2,output3]=[0,0,0] ; Г CASE Г condition41 : next_state41 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г condition42 : next_state42 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г condition43 : next_state43 Г WITH Г [output1,output2,output3]=[0,0,0] ; Г ENDWITH ; Г ENDCASE ; Г ГDECLARATIONS Г Г NS = [Q1,Q0] ; "NEXT STATE" Г ГTEST_VECTORS Г Г ([MR,CP,input1,input2,input3] -> [NS,output1,output2,output3]) Г ГEND РФ All the place holders were generated by ASTATER.EXE in lowercase letters. Using the replace function of your editor (a global replace) do the folowing replacements: page 7 - Replace input1 with U - Replace input2 with V - Replace input3 with W - Replace output1 with R - Replace output2 with S - Replace output3 with T Now do the folowing changes: - Make state assignments. for example: AA = [0,0], BB = [0,1], CC = [1,0], DD = [1,1] The assignment of combination [0,0] to state AA and the declarations of attributes 'REG,BUFFER' that were chosen for Q1 and Q0, make the AA state the reset state of the machine. It is not hard to change it. - Delete the WITH..ENDWITH blocks from first, third and last state blocks. These blocks desribe Mealy type behavior, and these blocks are Moore type blocks (only the second block describes a Mealy behavior). - Replace dummy conditions (condition1,condition2...) and next_states (next_state1, next_state2...) , with real conditions and real next_states and delete lines that are not needed. It is possible to describe an unconditional transition with ABEL's CASE statements in the following way: STATE DD : [R,S,T]=[1,1,0] ; CASE 1 : AA <- this is the unconditional transition ENDCASE ; it is equivalent to the folowing statements: STATE DD : [R,S,T]=[1,1,0] ; GOTO AA page 8 - Replace zero output assignments (Mealy and Moore type) with real (0 or 1) output assignments and delete output assignments that are not needed. - Add test vector values. Now the file will look like this: M1.ABL кФ ГMODULE M1 ГTITLE 'M1.ABL created by ASTATER.EXE Version 1.0 Г Time of creation is Sat Aug 20 17:07:13 1994 Г ' ГDECLARATIONS Г Г M1 DEVICE ; Г U PIN ; Г V PIN ; Г W PIN ; Г CP PIN ; "CLOCK INPUT" Г MR PIN ; "MASTER RESET (ASYN) INPUT" Г R PIN ISTYPE 'COM' ; Г S PIN ISTYPE 'COM' ; Г T PIN ISTYPE 'COM' ; Г Q1 NODE ISTYPE 'REG,BUFFER' ; Г Q0 NODE ISTYPE 'REG,BUFFER' ; Г Г PS = [Q1,Q0] ; "STATE ASSIGNMENT" Г AA = [ 0, 0] ; Г BB = [ 0, 1] ; Г CC = [ 1, 0] ; Г DD = [ 1, 1] ; Г Г C , X , P , Z = .C. , .X. , .P. , .Z. ; Г ГEQUATIONS Г Г PS.AR = !MR ; Г PS.CLK = CP ; Г page 9 ГSTATE_DIAGRAM PS Г Г STATE AA : Г [R,S,T]=[1,0,0] ; Г CASE Г !U : AA Г U : BB Г ENDCASE ; Г STATE BB : Г [R,S]=[0,1] ; Г CASE Г !V : CC Г WITH Г T = 1 ; Г ENDWITH ; Г V : DD Г WITH Г T = 0 ; Г ENDWITH ; Г ENDCASE ; Г STATE CC : Г [R,S,T]=[0,0,0] ; Г CASE Г !V & W : CC Г V & W : DD Г !W : AA Г ENDCASE ; Г STATE DD : Г [R,S,T]=[1,1,0] ; Г CASE Г 1 : AA Г ENDCASE ; Г ГDECLARATIONS Г Г NS = [Q1,Q0] ; "NEXT STATE" Г page 10 ГTEST_VECTORS Г Г ([MR,CP,U,V,W] -> [PS,R,S,T]) Г [ 0, X,X,X,X] -> [AA,1,0,0]; "RESET" Г [ 1, C,0,X,X] -> [AA,1,0,0]; "AA->AA" Г [ 1, C,1,X,X] -> [BB,0,1,X]; "AA->BB (T IS X)" Г [ 1, 0,X,0,X] -> [BB,0,1,1]; "BB/T" Г [ 1, 0,X,1,X] -> [BB,0,1,0]; "BB/!T" Г [ 1, C,X,0,X] -> [CC,0,0,0]; "BB->CC" Г [ 1, C,X,0,1] -> [CC,0,0,0]; "CC->CC" Г [ 1, C,X,X,0] -> [AA,1,0,0]; "CC->AA" Г [ 1, C,1,X,X] -> [BB,0,1,X]; "AA->BB (T IS X)" Г [ 1, C,X,1,X] -> [DD,1,1,0]; "BB->DD" Г [ 1, C,X,X,X] -> [AA,1,0,0]; "DD->AA" Г [ 1, C,1,X,X] -> [BB,0,1,X]; "AA->BB (T IS X)" Г [ 1, C,X,0,X] -> [CC,0,0,0]; "BB->CC" Г [ 1, C,X,1,1] -> [DD,1,1,0]; "CC->DD" Г [ 1, C,X,X,X] -> [AA,1,0,0]; "DD->AA" Г ГEND РФ Now compile, simulate and generate a JEDEC file using ABEL. page 11 Example 2 : A Mealy machine with One-Hot state assignment --------------------------------------------------------- In this example we will design the same state machine that we designed before, but we will use the One-Hot state assignment. for this kind of assignment we need 4 flip-flops. This time we will run ASTATER.EXE using the same command line parameters except the number of flip-flops that is 4 and the name of the machine that will be changed to M2. Here is how the command line looks: ASTATER M2 3 3 3 2 /2 AA BB CC DD The file that will be generated looks like the file we got earlier but with more flip-flops. All the replacements we did before will be done here too: - Replace input1 with U - Replace input2 with V - Replace input3 with W - Replace output1 with R - Replace output2 with S - Replace output3 with T The main difference between this example and the previous example, is in the state assignments. Write the following one-hot state assignments: AA = [1,0,0,0], BB = [0,1,0,0], CC = [0,0,1,0] DD = [0,0,0,1] Other important change that must be done (that differ from the previous example) is to change the declaration of node Q0 from ISTYPE 'REG,BUFFER' to ISTYPE 'REG,INVERT'. This change is done because we want the reset state to be AA [1,0,0,0]. When MR is invoked (MR is active-low) we want the machine to be in the AA state. In this state Q0 (the flip-flop of state AA) must be in a High (1) state. All the other changes we had to make in this example to the original ASTATER generated source file, are the same changes we had to do in the previous example. Here are all the changes that need to be done: - Delete WITH..ENDWITH blocks from first, third and last state blocks. These blocks describe Moore type behavior. - Replace dummy conditions (condition1,condition2...) and next_states (next_state1, next_state2...) with real conditions and real next_states and delete lines that are not needed. page 12 - Replace zero output assignments (Mealy and Moore type) with real output assignments and delete output assignments that are not needed. - Add test vector values. Now the file will look like this: M2.ABL кФ ГMODULE M2 ГTITLE 'M2.ABL created by ASTATER.EXE Version 1.0 Г Time of creation is Sat Aug 20 17:07:13 1994 Г ' ГDECLARATIONS Г Г M2 DEVICE ; Г U PIN ; Г V PIN ; Г W PIN ; Г CP PIN ; "CLOCK INPUT" Г MR PIN ; "MASTER RESET (ASYN) INPUT" Г R PIN ISTYPE 'COM' ; Г S PIN ISTYPE 'COM' ; Г T PIN ISTYPE 'COM' ; Г Q3 NODE ISTYPE 'REG,BUFFER' ; Г Q2 NODE ISTYPE 'REG,BUFFER' ; Г Q1 NODE ISTYPE 'REG,BUFFER' ; Г Q0 NODE ISTYPE 'REG,INVERT' ; Г Г PS = [Q3,Q2,Q1,Q0] ; "STATE ASSIGNMENT" Г AA = [ 0, 0, 0, 1] ; Г BB = [ 0, 0, 1, 0] ; Г CC = [ 0, 1, 0, 0] ; Г DD = [ 1, 0, 0, 0] ; Г Г C , X , P , Z = .C. , .X. , .P. , .Z. ; Г ГEQUATIONS Г Г PS.AR = !MR ; Г PS.CLK = CP ; Г page 13 ГSTATE_DIAGRAM PS Г Г STATE AA : Г [R,S,T]=[1,0,0] ; Г CASE Г !U : AA Г U : BB Г ENDCASE ; Г STATE BB : Г [R,S]=[0,1] ; Г CASE Г !V : CC Г WITH Г T = 1 ; Г ENDWITH ; Г V : DD Г WITH Г T = 0 ; Г ENDWITH ; Г ENDCASE ; Г STATE CC : Г [R,S,T]=[0,0,0] ; Г CASE Г !V & W : CC Г V & W : DD Г !W : AA Г ENDCASE ; Г STATE DD : Г [R,S,T]=[1,1,0] ; Г CASE Г 1 : AA Г ENDCASE ; Г ГDECLARATIONS Г Г NS = [Q1,Q0] ; "NEXT STATE" Г page 14 ГTEST_VECTORS Г Г ([MR,CP,U,V,W] -> [PS,R,S,T]) Г [ 0, X,X,X,X] -> [AA,1,0,0]; "RESET" Г [ 1, C,0,X,X] -> [AA,1,0,0]; "AA->AA" Г [ 1, C,1,X,X] -> [BB,0,1,X]; "AA->BB (T IS X)" Г [ 1, 0,X,0,X] -> [BB,0,1,1]; "BB/T" Г [ 1, 0,X,1,X] -> [BB,0,1,0]; "BB/!T" Г [ 1, C,X,0,X] -> [CC,0,0,0]; "BB->CC" Г [ 1, C,X,0,1] -> [CC,0,0,0]; "CC->CC" Г [ 1, C,X,X,0] -> [AA,1,0,0]; "CC->AA" Г [ 1, C,1,X,X] -> [BB,0,1,X]; "AA->BB (T IS X)" Г [ 1, C,X,1,X] -> [DD,1,1,0]; "BB->DD" Г [ 1, C,X,X,X] -> [AA,1,0,0]; "DD->AA" Г [ 1, C,1,X,X] -> [BB,0,1,X]; "AA->BB (T IS X)" Г [ 1, C,X,0,X] -> [CC,0,0,0]; "BB->CC" Г [ 1, C,X,1,1] -> [DD,1,1,0]; "CC->DD" Г [ 1, C,X,X,X] -> [AA,1,0,0]; "DD->AA" Г ГEND РФ Now compile, simulate and generate a JEDEC file using ABEL. page 15 Example 3 : A Moore machine with direct outputs ----------------------------------------------- In this example we will be designing the following Moore machine: кФФФФФФФФФФФФФФФТФФФФФФФФФТТФФФФФФФФФФФФФФФТФФФФФФФФФП Г Present State Г Input ГГ Next State Г Output Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г AA Г !U ГГ AA Г R Г Г Г U ГГ BB Г R Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г BB Г !V ГГ CC Г S,T Г Г Г V ГГ DD Г S,T Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г CC Г !V & W ГГ CC Г - Г Г Г V & W ГГ DD Г - Г Г Г !W ГГ AA Г - Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г DD Г 1 ГГ AA Г R,S Г РФФФФФФФФФФФФФФФСФФФФФФФФФССФФФФФФФФФФФФФФФСФФФФФФФФФй This machine has 3 inputs an 3 outputs and behaves almost exactly like the machine from the previous examples. The only difference is that the T output dose not change as a function of V, when the machine is in the BB state (it used to change on the first and second examples). In the previous examples the outputs of the machine were not directly the outputs of the flip-flops. Combinatorial logic was used to decode the flip-flop outputs combinations to machine output combinations (a waste of hardware resources). CP Ф>ФП кФФФФФФФФФФФФФФФФП Г кФФФФФФП Г Cmbinational УФХФ>ДD1 УФТФ Q1 Г Г УФФД> FF Г Г Г Sum of product Г Г РФФФФФФй Г Г УФХФФФФФ<ФФФФФй foldback U ФФФФФФ>Д Matrix Г Г кФФФФФФП Г УФХФ>ДD1 УФТФ Q0 V ФФФФФФ>Д Г РФФД> FF Г Г Г Г РФФФФФФй Г W ФФФФФФ>Д УФФФФФФФ<ФФФФФй foldback Г d Г Г e УФФФФФФФ>ФФФФФФФ R Г c Г Г o УФФФФФФФ>ФФФФФФФ S Г d Г Г e УФФФФФФФ>ФФФФФФФ T РФФФФФФФФФФФФФФФФй page 16 When a design of this type is implemented with a flip-flop that has no buried registers, it wastes pins (ABEL will automatically exchange NODEs to PINs if the device has no nodes). When designing a Moore machine, one can assign flip-flops so the outputs of machine will be directly the outputs of filp-flops. CP Ф>ФП кФФФФФФФФФФФФФФФФП Г кФФФФФФП Г Cmbinational УФХФ>ДDR УФТФ R Г Г УФФД> FF Г Г Г Sum of product Г Г РФФФФФФй Г Г УФХФФФФФ<ФФФФФй U ФФФФФФ>Д Matrix Г Г кФФФФФФП Г УФХФ>ДDS УФТФ S V ФФФФФФ>Д Г УФФД> FF Г Г Г Г Г РФФФФФФй Г W ФФФФФФ>Д УФХФФФФФ<ФФФФФй Г Г Г кФФФФФФП Г УФХФ>ДDT УФТФ T Г Г РФФД> FF Г Г Г Г РФФФФФФй Г Г УФФФФФФФ<ФФФФФй РФФФФФФФФФФФФФФФФй This will save pins of the PAL, reduce tpd (from the clock signal to the outputs), and produce clean outputs with no spikes. Not all outputs have to be produced this way. Some times a mixture of direct and indirect outputs is also chosen. In this example we want all outputs to come directly from flip-flop outputs. To do this we choose to define zero outputs in the command line of ASTATER. The number of outputs defined for ASTATER is the number of indirect outputs ! We also chose three flip-flops (a flip-flop for every output). This is the command and command line parameters used: ASTATER M3 3 0 3 3 /1 AA BB CC DD page 17 Here is the file that will be created by ASTATER.EXE : M3.ABL кФ ГMODULE M3 ГTITLE 'M3.ABL created by ASTATER.EXE Version 1.0 Г Time of creation is Sat Aug 20 17:07:13 1994 Г ' ГDECLARATIONS Г Г M3 DEVICE ; Г input1 PIN ; Г input2 PIN ; Г input3 PIN ; Г CP PIN ; "CLOCK INPUT" Г MR PIN ; "MASTER RESET (ASYN) INPUT" Г Q2 NODE ISTYPE 'REG,BUFFER' ; Г Q1 NODE ISTYPE 'REG,BUFFER' ; Г Q0 NODE ISTYPE 'REG,BUFFER' ; Г Г PS = [Q2,Q1,Q0] ; "STATE ASSIGNMENT" Г AA = [ 0, 0, 0] ; Г BB = [ 0, 0, 0] ; Г CC = [ 0, 0, 0] ; Г DD = [ 0, 0, 0] ; Г Г C , X , P , Z = .C. , .X. , .P. , .Z. ; Г ГEQUATIONS Г Г PS.AR = !MR ; Г PS.CLK = CP ; Г page 18 ГSTATE_DIAGRAM PS Г Г STATE AA : Г CASE Г condition11 : next_state11 Г condition12 : next_state12 Г condition13 : next_state13 Г ENDCASE ; Г STATE BB : Г CASE Г condition21 : next_state21 Г condition22 : next_state22 Г condition23 : next_state23 Г ENDCASE ; Г STATE CC : Г CASE Г condition31 : next_state31 Г condition32 : next_state32 Г condition33 : next_state33 Г ENDCASE ; Г STATE DD : Г CASE Г condition41 : next_state41 Г condition42 : next_state42 Г condition43 : next_state43 Г ENDCASE ; Г ГDECLARATIONS Г Г NS = [Q2,Q1,Q0] ; "NEXT STATE" Г ГTEST_VECTORS Г Г ([MR,CP,input1,input2,input3] -> NS ; Г ГEND РФ Notice that the Mealy output assignments are missing now from the file. page 19 All the replacements we did in previous examples are done here in the same way: - Replace input1 with U - Replace input2 with V - Replace input3 with W - There are no replacements for output1/2/3 because they were not generated in file The main difference between this implementation and the previous ones is in the state assignments. Write the following state assignments: AA = [1,0,0], BB = [0,1,1], CC = [0,0,0], DD = [1,1,0] In case a unique assignment for each state could not be found more flip-flops could be appended to the state register (we do not need to add flip-flops in this example). Other important change that must be made is to change node Q0 from ISTYPE 'REG,BUFFER'to ISTYPE 'REG,INVERT'. This is because we want the reset state to be AA. When MR is invoked (low) we want the machine to be in the AA state. In this state Q0 (the flip-flop that is a direct output implementing the R output of the machine) must be in a High (1) state. All the other changes we have to make to the original ASTATER generated file are the same changes we did in the previous examples. Here are all the changes that need to be done: - Replace dummy conditions (condition1, condition2...) and next_states (next_state1, next_state2...) with real conditions and next_states and delete lines that are not needed. - Add test vector values. page 20 Now the file will look like this: M3.ABL кФ ГMODULE M3 ГTITLE 'M3.ABL created by ASTATER.EXE Version 1.0 Г Time of creation is Sat Aug 20 17:07:13 1994 Г ' ГDECLARATIONS Г Г M3 DEVICE ; Г U PIN ; Г V PIN ; Г W PIN ; Г CP PIN ; "CLOCK INPUT" Г MR PIN ; "MASTER RESET (ASYN) INPUT" Г Q2 NODE ISTYPE 'REG,INVERT' ; Г Q1 NODE ISTYPE 'REG,BUFFER' ; Г Q0 NODE ISTYPE 'REG,BUFFER' ; Г Г PS = [Q2,Q1,Q0] ; "STATE ASSIGNMENT" Г AA = [ 1, 0, 0] ; Г BB = [ 0, 1, 1] ; Г CC = [ 0, 0, 0] ; Г DD = [ 1, 1, 0] ; Г Г C , X , P , Z = .C. , .X. , .P. , .Z. ; Г ГEQUATIONS Г Г PS.AR = !MR ; Г PS.CLK = CP ; Г ГSTATE_DIAGRAM PS Г page 21 Г STATE AA : Г CASE Г !U : AA Г U : BB Г ENDCASE ; Г STATE BB : Г CASE Г !V : CC Г V : DD Г ENDCASE ; Г STATE CC : Г CASE Г !V & W : CC Г V & W : DD Г !W : AA Г ENDCASE ; Г STATE DD : Г CASE Г 1 : AA Г ENDCASE ; Г ГDECLARATIONS Г Г NS = [Q2,Q1,Q0] ; "NEXT STATE" Г ГTEST_VECTORS Г Г ([MR,CP,U,V,W] -> NS) Г [ 0, X,X,X,X] -> AA; "RESET" Г [ 1, C,0,X,X] -> AA; "AA->AA" Г [ 1, C,1,X,X] -> BB; "AA->BB" Г [ 1, C,X,0,X] -> CC; "BB->CC" Г [ 1, C,X,0,1] -> CC; "CC->CC" Г [ 1, C,X,X,0] -> AA; "CC->AA" Г [ 1, C,1,X,X] -> BB; "AA->BB" Г [ 1, C,X,1,X] -> DD; "BB->DD" Г [ 1, C,X,X,X] -> AA; "DD->AA" Г [ 1, C,1,X,X] -> BB; "AA->BB" Г [ 1, C,X,0,X] -> CC; "BB->CC" Г [ 1, C,X,1,1] -> DD; "CC->DD" Г [ 1, C,X,X,X] -> AA; "DD->AA" Г ГEND РФ Now compile, simulate and generate a JEDEC file using ABEL. page 21 Example 4 : A Moore mixed example --------------------------------- In this example we will be designing the following Moore machine: кФФФФФФФФФП I ФФФ>Д УФФ>Ф P J ФФФ>Д УФФ>Ф Q Inputs K ФФФ>Д M4 УФФ>Ф R Outputs L ФФФ>Д УФФ>Ф S M ФФФ>Д УФФ>Ф T РФФФФТФФФФй Г Cp ФФ>ФФй кФФФФФФФФФФФФФФФТФФФФФФФФФТТФФФФФФФФФФФФФФФТФФФФФФФФФП Г Present State Г Input ГГ Next State Г Output Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г AA Г !I ГГ AA Г P Г Г Г I ГГ BB Г P Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г BB Г !J ГГ BB Г Q Г Г Г J ГГ CC Г Q Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г CC Г I $ J ГГ DD Г - Г Г Г I!$ J ГГ CC Г - Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г DD Г K # L ГГ EE Г R,T Г Г Г !K & !L ГГ DD Г R,T Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г EE Г !M ГГ EE Г S,T Г Г Г M ГГ FF Г S,T Г УФФФФФФФФФФФФФФФХФФФФФФФФФХХФФФФФФФФФФФФФФФХФФФФФФФФФД Г FF Г 1 ГГ AA Г R,S,T Г РФФФФФФФФФФФФФФФСФФФФФФФФФССФФФФФФФФФФФФФФФСФФФФФФФФФй page 22 This machine has 5 inputs an 5 outputs and behaves as a moore machine. Suppose we need that the outputs P,Q and T be clean outputs that do not produce decoding spikes (because they drive for example an asynchronous reset of a flip-flop or a write-enable input of a RAM) It is recommended to use a One-Hot state assignment for state A and B because the P and Q outputs are active only on state AA and BB. We will assign state AA to flip-flop Q2 and state BB to flip flop Q3. The outputs of the flip-flops Q2 and Q3 will be P and Q outputs respectively. The T output is not unique to only one state, so we will not be able to use a one hot assignment in order to produce it. We will just add a special flip-flop that will produce this output directly. This will be flip-flop Q4. The output of Q4 is the output T (T is a direct output). Suppose that the other outputs are allowed to have decoding spikes (because they drive for example other synchronous devices that share the same clock). Also suppose for example, that target device has unused buried nodes. We will want to use the buried nodes and not waste any more output macrocells of the device. We can choose to fully encode the other state combinations and assign them to a pair of flip-flops called Q1 and Q0. We will assign CC to [Q1,Q0] = [0,0], DD to [Q1,Q0] = [0,1], EE to [Q1,Q0] = [1,0] and FF to [Q1,Q0] = [1,1] When we use ASTATER.EXE we need only to declare to outputs (R and S), which are indirect outputs. All other outputs (P,Q and T) are direct flip-flop outputs. The total number of flip-flops will be 1 + 1 + 1 + 2 = 5. The number of states is 6 and number of transitions is 2. The number of inputs is 5. The command and command line parameters used in this example are: ASTATER M4 5 2 2 5 /1 AA BB CC DD EE FF page 23 Here is the file that will be created by ASTATER.EXE : M4.ABL кФ ГMODULE M4 ГTITLE 'M4.ABL created by ASTATER.EXE Version 1.0 Г Time of creation is Sat Aug 20 17:07:13 1994 Г ' ГDECLARATIONS Г Г M4 DEVICE ; Г input1 PIN ; Г input2 PIN ; Г input3 PIN ; Г input4 PIN ; Г input5 PIN ; Г CP PIN ; "CLOCK INPUT" Г MR PIN ; "MASTER RESET (ASYN) INPUT" Г output1 PIN ISTYPE 'COM' ; Г output2 PIN ISTYPE 'COM' ; Г Q4 NODE ISTYPE 'REG,BUFFER' ; Г Q3 NODE ISTYPE 'REG,BUFFER' ; Г Q2 NODE ISTYPE 'REG,BUFFER' ; Г Q1 NODE ISTYPE 'REG,BUFFER' ; Г Q0 NODE ISTYPE 'REG,BUFFER' ; Г Г PS = [Q4,Q3,Q2,Q1,Q0] ; "STATE ASSIGNMENT" Г AA = [ 0, 0, 0, 0, 0] ; Г BB = [ 0, 0, 0, 0, 0] ; Г CC = [ 0, 0, 0, 0, 0] ; Г DD = [ 0, 0, 0, 0, 0] ; Г EE = [ 0, 0, 0, 0, 0] ; Г FF = [ 0, 0, 0, 0, 0] ; Г Г C , X , P , Z = .C. , .X. , .P. , .Z. ; Г ГEQUATIONS Г Г PS.AR = !MR ; Г PS.CLK = CP ; Г page 24 ГSTATE_DIAGRAM PS Г Г STATE AA : Г [output1,output2] = [0,0] ; Г CASE Г condition11 : next_state11 Г condition12 : next_state12 Г ENDCASE ; Г STATE BB : Г [output1,output2] = [0,0] ; Г CASE Г condition21 : next_state21 Г condition22 : next_state22 Г ENDCASE ; Г STATE CC : Г [output1,output2] = [0,0] ; Г CASE Г condition31 : next_state31 Г condition32 : next_state32 Г ENDCASE ; Г STATE DD : Г [output1,output2] = [0,0] ; Г CASE Г condition41 : next_state41 Г condition42 : next_state42 Г ENDCASE ; Г STATE EE : Г [output1,output2] = [0,0] ; Г CASE Г condition51 : next_state51 Г condition52 : next_state52 Г ENDCASE ; Г STATE FF : Г [output1,output2] = [0,0] ; Г CASE Г condition61 : next_state61 Г condition62 : next_state62 Г ENDCASE ; Г ГDECLARATIONS Г Г NS = [Q4,Q3,Q2,Q1,Q0] ; "NEXT STATE" Г ГTEST_VECTORS Г Г ([MR,CP,input1,input2,input3,input4,input5] -> [NS,output1,output2]) Г ГEND РФ page 25 Here is the file after making changes with an editor: M4.ABL кФ ГMODULE M4 ГTITLE 'M4.ABL created by ASTATER.EXE Version 1.0 Г Time of creation is Sat Aug 20 17:07:13 1994 Г ' ГDECLARATIONS Г Г M4 DEVICE ; Г I PIN ; Г J PIN ; Г K PIN ; Г L PIN ; Г M PIN ; Г CP PIN ; "CLOCK INPUT" Г MR PIN ; "MASTER RESET (ASYN) INPUT" Г R PIN ISTYPE 'COM' ; Г S PIN ISTYPE 'COM' ; Г Q4 PIN ISTYPE 'REG,BUFFER' ; Г Q3 PIN ISTYPE 'REG,BUFFER' ; Г Q2 PIN ISTYPE 'REG,INVERT' ; Г Q1 NODE ISTYPE 'REG,BUFFER' ; Г Q0 NODE ISTYPE 'REG,BUFFER' ; Г Г PS = [Q4,Q3,Q2,Q1,Q0] ; "STATE ASSIGNMENT" Г AA = [ 0, 0, 1, 0, 0] ; Г BB = [ 0, 1, 0, 0, 0] ; Г CC = [ 0, 0, 0, 0, 0] ; Г DD = [ 1, 0, 0, 0, 1] ; Г EE = [ 1, 0, 0, 1, 0] ; Г FF = [ 1, 0, 0, 1, 1] ; Г Г C , X , P , Z = .C. , .X. , .P. , .Z. ; Г ГEQUATIONS Г Г PS.AR = !MR ; Г PS.CLK = CP ; Г page 26 ГSTATE_DIAGRAM PS Г Г STATE AA : Г [R,S] = [0,0] ; Г CASE Г !I : AA Г I : BB Г ENDCASE ; Г STATE BB : Г [R,S] = [0,0] ; Г CASE Г !J : BB Г J : CC Г ENDCASE ; Г STATE CC : Г [R,S] = [0,0] ; Г CASE Г I $ J : DD Г I !$ J : CC Г ENDCASE ; Г STATE DD : Г [R,S] = [1,0] ; Г CASE Г K # L : EE Г !K & !L : DD Г ENDCASE ; Г STATE EE : Г [R,S] = [0,1] ; Г CASE Г !M : EE Г M : FF Г ENDCASE ; Г STATE FF : Г [R,S] = [1,1] ; Г CASE Г 1 : AA Г ENDCASE ; Г ГDECLARATIONS Г Г NS = [Q4,Q3,Q2,Q1,Q0] ; "NEXT STATE" Г page 27 ГTEST_VECTORS Г Г ([MR,CP,I,J,K,L,M] -> [NS,R,S]) Г [ 0, X,X,X,X,X,X] -> [AA,0,0]; "P IS 1" Г [ 1, C,0,X,X,X,X] -> [AA,0,0]; "P IS 1" Г [ 1, C,1,X,X,X,X] -> [BB,0,0]; "Q IS 1" Г [ 1, C,X,0,X,X,X] -> [BB,0,0]; "Q IS 1" Г [ 1, C,X,1,X,X,X] -> [CC,0,0]; Г [ 1, C,0,0,X,X,X] -> [CC,0,0]; Г [ 1, C,1,1,X,X,X] -> [CC,0,0]; Г [ 1, C,0,1,X,X,X] -> [DD,1,0]; Г [ 1, C,X,X,0,0,X] -> [DD,1,0]; "T IS 1" Г [ 1, C,X,X,1,1,X] -> [EE,0,1]; "T IS 1" Г [ 1, C,X,X,0,0,0] -> [EE,0,1]; "T IS 1" Г [ 1, C,X,X,0,0,1] -> [FF,1,1]; "T IS 1" Г [ 1, C,X,X,X,X,X] -> [AA,0,0]; "P IS 1" ГEND РФ The following changes were made: input1 -> I input2 -> J input3 -> K input4 -> L input5 -> M output1 -> R output2 -> S State Assignment: AA = [ 0, 0, 1, 0, 0] ; BB = [ 0, 1, 0, 0, 0] ; CC = [ 0, 0, 0, 0, 0] ; DD = [ 1, 0, 0, 0, 1] ; EE = [ 1, 0, 0, 1, 0] ; FF = [ 1, 0, 0, 1, 1] ; Inserting the true outputs of R & S Inserting transition conditions Changing attribute of Q2 from 'REG,BUFFER' to 'REG,INVERT' Changing signal type of Q4,Q3 and Q2 from NODE to PIN Adding test vector values page 28 Errors, Warning & Note Messages ------------------------------- If any error occurs the program will abort execution. Some errors will generate a help screen. this is the help screen: ------------------------------------usage------------------------------------- ASTATER /1|2 ... ---------------------------------parameters----------------------------------- .........................Module name \(file_name = module_name.ABL ...............................................Number of input signals ..............Number of output signals that are not flip-flop outputs ......................Maximum number of relevant condition per state ..................................................Number of flip-flops /1|2|3...................Machine type : /1 - Moore , /2 - Mealy , /3 Dummy .........................A list of state names (two or more) ------------------------------------------------------------------------------ Here is a the list of errors that the program can report: Error (1) : Define number of inputs. The number of inputs parameter is not defined correctly. It has to be an integer. Error (2) : Define number of outputs. The number of outputs parameter is not defined correctly. It has to be an integer. Error (3) : Define maximum number of transition conditions. The maximum number of outputs parameter is not defined correctly. It has to be an integer. Error (4) : Define number of flip flops. The number of flip-flops parameter is not defined correctly. It has to be an integer. Error (5) : Define machine type - moore (/1) or Mealy. The type of the machine is not defined correctly. It has to be a foreslash (/) followed by an integer. page 29 Error (6) : Machine type 'n' is an unknown machine_type. The type of the machine number is not defined correctly. It has to be a /1 (Moore) or /2 (Mealy). Error (7) : Can't create file 'file_name' for writing. Error (8) : Autonomous state machine is not supported. Autonomous transitions are supported, but only if they are not global. Read on previous text how to describe Autonomous transitions using the CASE..ENDCASE syntax. Error (9) : Too many inputs. The maximum number of allowed inputs is 30. Error (10) : Too many outputs. The maximum number of allowed outputs is 30. Error (11) : Calculated number of transition conditions is too big. Defined number of transition conditions by user was zero. In a situation like this the software normally chooses a number that is equal to (2)^(number_of_inputs). In this case the calculated number is too big. Error (12) : Too many transition conditions. The maximum number of allowed conditions is 4096. Error (13) : No flip-flops in machine. A state machine with no Flip-Flops is not a state machine. It is a combinatorial system. Error (14) : Too many flip-flops. A maximum of 30 flip-flops is allowed. page 30 Error (15) : 'n' states can not be assigned to only 'm' flip-flop(s). If for example you tried to declare tow flip-flops and six states it will not be possible to assign all six states to only four possible flip-flop combinations. This is because tow flip flops can decode only four states. Error (16): Missing command line parameter(s). The minimum number of command line parameters must be at least 7: - number of inputs - number of outputs - maximum number of input conditions - number of flip-flops - machine type - a first state name - a second state name Error (17): A Mealy type machine with no indirect outputs. Declaration of a mealy machine with no outputs is impossible because a mealy machine must have at least one output that depends on an input and not only on flip-flops. Here is a list of Errorlevel that are set when exiting the program: 0 - Successful execution 1 - Bad numeric values of parameters 2 - Bad definition of parameters 3 - File Overwrite not allowed 4 - File write problems Warnings & Notes will not be followed by aborting of execution. Warnings are for making you pay attention because some thing bad might be going on. Notes are only for informing you. page 31 Here is a list of Warnings that the program can report: Warning (1) : Output file 'file_name' already exists. The user has an option to Overwrite it (by hitting the key) or to abort (hitting any other key) Warning (2) : Zero outputs. Zero outputs is possible because all outputs of the machine can come directly from flip-flop outputs. In these cases it is possible for the designer to enter zero as the number of outputs (using the 0 command line parameter). Warning (3) : The number of transition conditions was changed from 'm' to 'n'. If the number that defined transition conditions was zero, and the user defined a number of inputs that is greater then zero, the software will generate a canonical number of transition conditions = (2)^(number_of_inputs). This can be a large number. Other cases when this warning is reported are when the maximum number of defined state transitions is higher than it is possible with the defined number of inputs. For example if the the user defined tow inputs and five conditions a warning will be reported. It will tell you that the maximum number of conditions was decreased, to four conditions (the maximum possible number of conditions when the machine has tow inputs). Here is a list of Notes that the program can report: Note (1) : Machine type is Moore. Note (2) : Machine type is Mealy. Note (3) : Number of un-used states is: 'n'. The program calculates the difference between the largest number off possible flip-flop combinations and the actual number of states that was defined. The designer has to pay attention to these Hang-Up states. The machine can enter a Hang-Up state during power-up or as a result of noise. page 32 Limitations & Legal details --------------------------- The software is written by and Copyrighted to - Amos Zaslavsky. ASTATER is a shareware. This means that you are allowed to copy it freely, and give copies to other users. You are encouraged to do so, but with the following limitations: - You must distribute ASTATER.EXE and ASTATER.DOC together and unmodified. - You may not charge more than a minimal distribution fee (maximum $5.00) for covering disk price & postage of a diskette containing the files. - You may not distribute ASTATER with or as part of other commercially sold software without written permission of the author. - You are not permitted to sell this program for profit in any way, shape or form. - If you like this program and use it regularly, the author would appreciate a contribution of $25.00, sent to the address below. - As with all shareware, these contributions are the incentives for the author to continue developing this utility and other utilities. - Contributors suggestions for enhancements will be considered in future versions. - The author would appreciate being informed of any bugs ! - Future enhancements may include improovments like ABEL Symbolic-state style, entering input & output names, an interactive version, and other HDL's like PALASM and CUPUL or even C. My address is: Amos Zaslavsky 28 Berel Katzenelson st. Haifa Israel 32768 Telephone (voice): 972-4-230219 Thank you.